The invention relates to a structure for providing electrical interconnection between levels formed at different heights in an integrated circuit, specifically to elements in a dense multilevel array.
It is known to form vias to electrically connect routing levels formed at different heights in an integrated circuit. In a conventional arrangement, shown in FIG. 1, bottom routing level RL1 is formed first. Generally a dielectric material is deposited on RL1. The dielectric material is selectively excavated to form a hole, which is then filled with a conductive material to form via V1. In the same manner routing level RL2 is formed above via V1, via V2 formed above routing level RL2, and so on, alternating routing levels and vias providing electrical interconnection as required.
With the advent of extremely dense structures requiring extensive interconnection, including, for example, interconnection between layers that are not vertically adjacent, while the highest possible density must be maintained, this conventional arrangement uses space inefficiently and requires extra processing steps.
There is a need, therefore, to form vias between different levels in a dense array while using as little die area as possible.